1. Field of the Invention
The present invention relates to an analog-to-digital converter (ADC) for converting an analog signal into a digital signal.
2. Description of the Related Art
As an ADC with low power consumption, a successive comparative ADC with a capacitive D/A converter (capacitive DAC) is known. The successive comparative ADC includes a plurality of capacitors which are binarily weighted in capacitance and connected in parallel to one another, a plurality of switching elements for controlling the interconnections of the capacitors, a comparator comprised of an amplifier and a latch circuit and a logic circuit for generating a switching control signal. It takes long period of time for the successive comparative ADC to realize high resolution. In order to constitute the successive comparative ADC as a high resolution ADC, it is also required for the successive comparative ADC to have a large area corresponding to the number of capacitor.
On the other hand, a pipelined successive comparative ADC is proposed where the conversion period of time of the successive comparative ADC can be shortened and the area corresponding to the number of capacitor can be reduced even though the successive comparative ADC is constituted as a high resolution ADC. The pipelined successive comparative ADC includes a first successive comparative ADC for implementing a rough A/D conversion, a second successive comparative ADC for implementing a fine A/D conversion and an intermediate residue calculating circuit comprised of an amplifier and a capacitive DAC. In this way, the pipelined successive comparative ADC requires two successive comparative ADCs serially connected with one another and the capacitive DAC to perform D/A conversion of the converted value by the first successive comparative ADC in addition to the inherent capacitive DACs contained in the two successive comparative ADCs. Therefore, the number of capacitor of the entire circuit containing the pipelined successive comparative ADC is relatively increased so that the circuit area is also increased (see U.S. Pat. No. 6,124,818). In this way, there is such a problem that the circuit areas of the conventional successive comparative ADCs and the conventional pipelined successive comparative ADCs are enlarged due to the increase of the number of capacitors.